Bipolar transistor and method for fabricating it

ABSTRACT

The method according to the invention makes it possible to fabricate a bipolar transistor with a low base connection resistance, low defect density and improved scalability. Scalability is to be understood in this case as both the lateral scaling of the emitter window and the vertical scaling of the base width (low temperature budget). The temperature budget can be kept low in the base region since no implantations are required in order to reduce the base connection resistance. Furthermore, the difficulties associated with the point defects are largely avoided.

[0001] The present invention relates to a bipolar transistor.Furthermore, the invention relates to a method for fabricating a bipolartransistor.

[0002] Bipolar transistors are generally constructed from two pnjunctions lying close together in a semiconductor crystal. In this case,either two n-doped regions are isolated from one another by a p-dopedregion (so-called npn transistors) or two p-doped regions are isolatedfrom one another by an n-doped region (pnp transistors). The threedifferently doped regions are designated as emitter (E), base (B) andcollector (C). Bipolar transistors have already been known for a longtime and are used in manifold ways. A distinction is made betweenso-called individual transistors, which are intended for mounting onprinted circuit boards or the like and are accommodated in their ownhousing, and so-called integrated transistors, which are fabricatedtogether with further semiconductor components on a common semiconductorcarrier, generally designated as substrate.

[0003] The maximum oscillation frequency f_(max) of a bipolar transistoris proportional to the root of f_(T) divided by 8πR_(B)C_(BC), whereR_(B) is the base resistance, C_(BC) is the base-collector capacitanceand f_(T) is the transition frequency. In order to obtain highoscillation frequencies, it is desirable, therefore, to reduce the baseresistance. The base resistance of a bipolar transistor is determinedboth by the resistance of the connection region and by the sheetresistance of the base doping profile. This sheet resistance, theso-called pinch, is inversely proportional to the base thickness givenhomogenous base doping. However, an increase in the base thickness leadsto lengthening of the base transit time for the minority carriers.

[0004] An increase in the homogeneous base doping above 5 10¹⁸ reducesthe breakdown voltage of the emitter-base junction to excessively lowvalues and simultaneously increases the capacitance of the base-emitterdepletion layer. A known method for further reducing the base pinchresistance is the use of a lightly doped (1 10¹⁸), epitaxial emitter.The light emitter doping allows the base to be doped practically up to 110²⁰ without the blocking capability of the emitter-base junction beinglost. Owing to the increased base charge compared with the emitter, thecurrent gain of such a transistor would be too low, but this can becompensated for by the use of germanium in the base.

[0005] Previous concepts for producing structures with an epitaxialemitter are illustrated and described for example in Behammer et al.,Solid State Electronics Vol 41, No. 8, pp. 1105-1110 (1997) or J. Schizet al. IEEE (1997), ISBN 7803-4135-X, pp. 255-260.

[0006]FIG. 14 diagrammatically shows a bipolar transistor in accordancewith the publication by Behammer et al. in a simplified manner. Thebipolar transistor first of all has a collector 102, which is formed ina silicon substrate or in a silicon epitaxial layer. The SiGe base 104(p-doped) is provided on the collector 102 (n-doped) and the n⁻typeemitter 106 is provided on the base 104. A p⁺-type implantation 108 isarranged in a manner laterally adjoining the collector 102, the base 104and the n⁻-type emitter 106, said implantation producing the contact tothe p-doped base. For the connection of the p⁺-type implantation 108, ametal layer 110 is provided, which is insulated from an n⁺-type emitter114 by a so-called sidewall spacer 112. The n⁺-type emitter 114 in turnis arranged above the n⁻-type emitter 106. The entire bipolar transistoris insulated from further components by an insulation 116 and aninsulation layer 118.

[0007] In accordance with the publication by Behammer et al., thebipolar transistor shown in FIG. 14 can be fabricated with the aid ofthe so-called “blanket epitaxy”. In this method, however, dry etching iseffected on the base connection region.

[0008]FIG. 15 diagrammatically shows a bipolar transistor in accordancewith the publication by J. Schiz et al. in a simplified manner. Thebipolar transistor 100 likewise has a collector 102 which is formed in asilicon substrate or in a silicon epitaxial layer. The SiGe base 104(p-doped) is provided on the collector 102 (n-doped) and the n⁻-typeemitter 106 is provided on the base 104. A p⁺-doped polysilicon layer120 is arranged in a manner laterally adjoining the base 104 and then⁻-type emitter 106, said polysilicon layer producing the contact to thep-doped base. An n⁺-type emitter 114 bounded by an aligned sidewallspacer 122 is arranged above the n⁻-type emitter 106. The entire bipolartransistor is again insulated from further components by an insulation116 and an insulation layer 118.

[0009] The bipolar transistor in accordance with the publication by J.Schiz et al. has to produce the sidewall spacer 122 by means of aphototechnology, with the result that a thickness of less than 200 μm isgenerally not possible. However, such a thick sidewall spacer 122results in significantly increased parasitic capacitances.

[0010] A common feature shared by the bipolar transistors shown in FIGS.14 and 15 is that a so-called “link implantation” (contact implantation)is carried out outside the emitter region in order to reduce the baseconnection resistance. In a further publication by Harame et al., Trans.ED Vol. 42, No. 3, pp. 469-482, FIG. 3 therein illustrates theimplantation damage, point defects, which are generally produced in thecase of such implantation, and also in the case of dry etching onsilicon substrate.

[0011] Even assuming that the point defects are not extended into theactive base region, the point defects present nonetheless lead to anabnormally high diffusion of the dopant boron into the nearby SiGe base104. In order to prevent such dopant diffusion, the sidewall spacercannot be made arbitrarily thin. In order to keep the point defects awayfrom the base, a sidewall spacer of approximately 150 nm or larger isnecessary, which, however, increases the link resistance and thebase-collector capacitance. For the case where the sidewall spacer iscompletely omitted and implantation is additionally effected into theconnection region, a functioning component cannot be expected.Furthermore, the base profile is greatly widened during subsequenttemperature steps above 550° C. on account of the point defects stillpresent.

[0012] The object of the present invention, therefore, is to provide abipolar transistor and also a method for fabricating it whichsignificantly reduces or completely avoids the difficulties outlined. Inparticular, the object of the present invention is to provide a bipolartransistor which has a low base connection resistance and also a lowdefect density.

[0013] This object is achieved by the method for fabricating a bipolartransistor in accordance with patent claim 1 and also by the bipolartransistor in accordance with patent claim 10. Further advantageousembodiments, refinements and aspects of the present invention emergefrom the subclaims, the description and the accompanying drawings.

[0014] The invention provides a method for fabricating a bipolartransistor, in particular an npn bipolar transistor, having thefollowing steps:

[0015] a) a semiconductor substrate with a collector, a base and alightly doped emitter layer is provided;

[0016] b) a mask is applied to the lightly doped emitter layer;

[0017] c) the lightly doped emitter layer is etched wet-chemically withthe aid of the mask, thereby forming a lightly doped emitter;

[0018] d) the base connection is formed on the uncovered regions of thebase;

[0019] e) the mask is removed and a highly doped emitter is formed.

[0020] Furthermore, the invention provides a bipolar transistor, inparticular an npn bipolar transistor, with a semiconductor substrate, acollector, a base, a lightly doped emitter and a highly doped emitter.The bipolar transistor according to the invention is characterized inthat the connection to the base is oriented essentially parallel to thelightly doped emitter and is isolated from the lightly doped emitter bya sidewall spacer or a pn junction.

[0021] The method according to the invention makes it possible tofabricate a bipolar transistor with a low base connection resistance,low defect density and improved scalability. Scalability is to beunderstood in this case as both the lateral scaling of the emitterwindow and the vertical scaling of the base width (low temperaturebudget). The temperature budget can be kept low in the base region sinceno implantations are required in order to reduce the base connectionresistance. Furthermore, the difficulties associated with the pointdefects are largely avoided.

[0022] In accordance with one preferred embodiment, a highly dopedsilicon-germanium base is used as the base. The use of germanium in thebase makes it possible to ensure an adequate current gain of the bipolartransistor despite an increased base charge.

[0023] The base preferably has a thickness of 20 to 50 nm and also adoping, in particular a p⁺-type doping, of more than 2 10¹⁹ per cubiccentimeter. Furthermore, it is preferred for the lightly doped emitterto have a thickness of 50 to 150 nm and also an n⁻-type doping of lessthan 2 10¹⁸ per cubic centimeter.

[0024] In accordance with a further preferred embodiment, the maskcomprises an oxide layer, a silicon layer and a nitride layer. In thiscase, it is preferred for the oxide layer (oxide stop layer) to beapplied to the lightly doped emitter layer with the aid of a CVD method.The thickness of the stop layer is preferably 5 to 30 nm. A, preferablyp⁺-doped, amorphous silicon layer having a thickness of 100 to 1000 nmis applied to the oxide layer. The nitride layer follows, which isdeposited by means of a sputtering method with a thickness of 20 to 50nm. The combined layer comprising nitride and amorphous silicon cansubsequently be patterned by phototechnology to the width of the emitterwindow by dry etching. The oxide layer in this case serves as an etchingstop, since amorphous silicon can be etched highly selectively (>10)with respect to oxide. The oxide can subsequently be removed by HF.

[0025] It is furthermore preferred for the lightly doped emitter layerto be etched wet-chemically using an alkaline etchant, in particularKOH, choline and/or ethylenediamine. Wet-chemical etching using analkaline etchant, in particular KOH, choline and/or ethylenediamine, hasthe advantage that etching is effected selectively between n-type andp-type silicon. The lightly doped emitter layer can thus be patternedselectively with respect to the base. Furthermore, wet-chemical etchinghas the advantage that no defects are produced in the underlying base inthis case.

[0026] In accordance with a further preferred embodiment, the lightlydoped emitter layer is formed above the base as an essentiallymonocrystaline layer and the wet-chemical etching stops on (111) facesin said essentially monocrystaline layer. Wet-chemical etching using KOHor choline, in particular, has the advantage that the etching stops on(111) faces which form during undercutting along (110) edges on a (100)surface. This is also the customary flat and substrate orientation insilicon wafers.

[0027] In accordance with a further preferred embodiment, a sidewallspacer, preferably a nitride spacer, is produced before the wet-chemicaletching on the side walls of the mask.

[0028] In accordance with a further preferred embodiment, a sidewallspacer, preferably a nitride spacer, is produced before the formation ofthe base connection on the side walls of the mask and of the lightlydoped emitter. In order to avoid dry etching on the base in this case,too, firstly the nitride layer, preferably 5 to 50 nm, is deposited andthen an oxide spacer is produced by dry etching. The nitride is thenremoved wet-chemically, preferably by phosphoric acid, selectively withrespect to the oxide, with the result that only the regions of thenitride layer which are protected by the oxide spacer remain. If theoxide spacer is subsequently removed using HF, these regions of thenitride layer form the sidewall spacer.

[0029] In accordance with a further preferred embodiment, the baseconnection is formed by means of differential epitaxy on the uncoveredregions of the base. In this case, it is particularly preferred for ahighly doped (>1 10²⁰), in particular a p⁺-doped, base connection to beused as the base connection. In this case, the selective epitaxy ispreferably effected at approximately the temperature at which the baseitself was also produced (for example approximately 800° C.).Accordingly, the doping profiles are not significantly widened in thiscase.

[0030] In accordance with a further preferred embodiment, a sidewallspacer, preferably a nitride spacer, is produced before the formation ofthe highly doped emitter on the side walls of the emitter window.

[0031] The invention is illustrated in more detail below with referenceto the figures of the drawings, in which

[0032] FIGS. 1 to 9 show a diagrammatic illustration of a firstembodiment of the method according to the invention,

[0033] FIGS. 10 to 13 show a diagrammatic illustration of a secondembodiment of the method according to the invention,

[0034]FIG. 14 diagrammatically shows a bipolar transistor in accordancewith the publication by Behammer et al. in a simplified manner, and

[0035]FIG. 15 diagrammatically shows a bipolar transistor in accordancewith the publication by J. Schiz et al. in a simplified manner.

[0036] FIGS. 1 to 9 below show a diagrammatic illustration of a firstembodiment of the method according to the invention. In accordance withstep a) of the method according to the invention, a silicon substrate 10with a collector 12, a base 14 and a lightly doped emitter 16 isprovided. In order to ensure the electrical connection of the collector12, the collector 12 is in contact with a buried layer 11. Furthermore,an insulation 17, a LOCOS insulation in the present example, and aso-called “channel stop” 18 beneath the insulation 17 are provided inorder to insulate the later bipolar transistor.

[0037] Proceeding from the silicon substrate 10 with the buried layer11, the collector 12 is produced on the buried layer 11, for example byselective epitaxy. In this case, the collector 12 is laterally boundedby an insulation layer 19, for example a TEOS layer. Afterward, a highlydoped silicon-germanium base 14 and a lightly doped emitter layer 16 aredeposited, for example by differential epitaxy. The base 14 preferablyhas a thickness of 20 to 50 nm and also a p⁺-type doping of more than 210¹⁹ per cubic centimeter. The lightly doped emitter 16 has a thicknessof 50 to 150 nm and also an n⁻-type doping of less than 2 10¹⁸ per cubiccentimeter. The resultant situation is shown in FIG. 1.

[0038] A CVD oxide stop layer 20 is subsequently deposited. In thiscase, the thickness of the oxide stop layer 20 is between 5 and 30 nm.The deposition is effected at a temperature of 600° C., for example. Ahighly doped (P⁺) amorphous silicon layer 21 is then deposited. In thiscase, the thickness of the amorphous silicon layer 21 is between 100 and1000 nm. The deposition is effected at a temperature of 550° C., forexample. Furthermore, a sputtered nitride layer 22 having a thickness ofabout 35 nm is applied.

[0039] Afterward, the nitride layer 22 and the amorphous silicon layer21 are patterned by phototechnology to the width of the emitter windowby dry etching. The oxide layer 20 serves as an etching stop in thiscase, since amorphous silicon can be etched highly selectively (>10)with respect to oxide. The oxide 20 will subsequently be removed by HF.The resultant situation is shown in FIG. 2.

[0040] An essential part of the method according to the invention nowconsists in patterning the lightly doped emitter layer 16 above the base14 by wet etching. The layer stack comprising oxide layer 20, amorphoussilicon layer 21 and nitride layer 22 in this case acts as a mask forthe patterning. In this case, it is preferred for the lightly dopedemitter layer 16 to be etched wet-chemically using KOH or choline.Wet-chemical etching using KOH or choline has the advantage that KOH orcholine etches selectively between n-type and p-type silicon. Thelightly doped emitter layer 16 can thus be patterned selectively withrespect to the base 14 and the already patterned amorphous silicon layer21. Furthermore, wet-chemical etching using KOH or choline has theadvantage that no defects are produced in the underlying base 14 in thiscase.

[0041] Since the lightly doped emitter layer 16 is formed above the base14 as an essentially monocrystaline layer, the wet-chemical etchingusing KOH or choline stops on (111) faces which form during undercuttingalong (110) edges on a (100) surface. This is also the customary flatand substrate orientation in silicon wafers. The lightly doped emitter16, which is bounded laterally (up to corner regions as well) by (111)faces is formed in this way. The resultant situation is shown in FIG. 3.

[0042] The side wall of the lightly doped emitter is then insulated by anitride spacer 23. In order to avoid dry etching on the base 14 in thiscase, too, firstly the nitride layer 23 having a thickness of between 5and 50 nm is deposited and then an oxide spacer 24 is patterned by oxidedeposition, for example TEOS, and subsequent dry etching. The resultantsituation is shown in FIG. 4. For reasons of simplicity, the (111) stopfaces which laterally bound the lightly doped emitter 16 are no longerillustrated in FIG. 4 and in the following figures.

[0043] Afterward, the nitride layer 23 is removed wet-chemically,preferably by phosphoric acid, selectively with respect to the oxide 24,with the result that only the regions of the nitride layer 23 which areprotected by the oxide spacer 24 remain. The oxide spacer 24 issubsequently removed using HF, with the result that said regions of thenitride layer which are protected by the oxide spacer form the sidewallspacer 23. The resultant situation is shown in FIG. 5.

[0044] Afterward, the base connection 25 is formed by means ofdifferential epitaxy on the uncovered regions of the base. In this case,it is particularly preferred for a highly doped (>1 10²⁰), in particulara P+-doped, base connection 25 to be used as the base connection. Inthis case, the selective epitaxy is preferably effected at approximatelythe temperature at which the base 14 itself was also produced (forexample approximately 800° C.). Accordingly, the doping profiles are notsignificantly widened in this case. The resultant situation is shown inFIG. 6.

[0045] The connection 25 to the base is thus oriented essentiallyparallel to the lightly doped emitter 16, i.e. the essential contactarea with which the base 14 is in contact with the base connection 25 isoriented parallel to the contact area with which the lightly dopedemitter 16 is in contact with the base 14. In this case, the baseconnection 25 is isolated from the lightly doped emitter by the sidewallspacer 23. Since the monocrystaline region of the base connection 25 isessentially free of defects, it is possible to make the sidewall spacer23 very thin.

[0046] As shown in FIG. 7, a CVD oxide 26 is then deposited andplanarized. In this case, the residual nitride layer 22 above theemitter window is polished away. Then this is followed by theself-aligned removal of the sacrificial layers in the emitter window. Inthis case, the amorphous silicon layer 21 is removed in the emitterwindow by dry etching, the for instance CVD oxide 20 again serving as anetching stop (FIG. 8).

[0047] After the oxide layer 20 has likewise been removed by wet etchingusing HF, the n+ emitter poly 27 is deposited and patterned. The basecontact 28 and also the collector contact 29 are subsequently producedin a customary manner. The resultant situation is shown in FIG. 9.

[0048] In contrast to the bipolar transistor according to the prior artas shown in FIG. 14, the bipolar transistor according to the inventionas shown in FIG. 9 has a sidewall spacer 23 which continues downward asfar as the base and is at least partly surrounded by an essentiallymonocrystaline base connection 25. In the case of the bipolar transistoraccording to the prior art as shown in FIG. 14, the monocrystalinep⁺-doped region terminates level with the n-type emitter and reachesdeep below the base, whereas in the case of the bipolar transistoraccording to the invention as shown in FIG. 9, the insulation begins onthe lower edge of the base and the monocrystaline region of the baseconnection 25 lies reliably above the upper edge of the base. Since themonocrystaline base connection 25 to the base 14 is essentially free ofdefects, it is possible to make the sidewall spacer 23 very thin.

[0049] FIGS. 10 to 13 below show a diagrammatic illustration of a secondembodiment of the method according to the invention. In this case, thefirst process steps of this second embodiment correspond to the processsteps which have already been described in connection with FIGS. 1 and2, so that a repetition can be dispensed with.

[0050] After the patterning of the nitride layer 22 and the amorphoussilicon layer 21 by dry etching, a nitride spacer 30 is produced on theside walls of the nitride layer 22 and of the amorphous silicon layer21. The oxide layer 20 again serves as an etching stop in this case. Theresultant situation is shown in FIG. 10. Instead of a layer stackcomprising silicon and silicon nitride, it is also possible to use amask composed exclusively of silicon nitride. This would have theadvantage that only two materials would need to be etched selectivelywith respect to one another. The oxide 20 is subsequently removed usingHF.

[0051] Afterward, it will necessary to pattern the lightly doped emitterlayer 16 above the base 14 by wet etching. The layer stack comprisingoxide layer 20, amorphous silicon layer 21 and nitride layer 22 in thiscase acts as a mask for the patterning. In this case, it is againpreferred for the lightly doped emitter layer 16 to be etchedwet-chemically using KOH or choline. Since the lightly doped emitterlayer 16 is formed above the base 14 as an essentially monocrystalinelayer, the wet-chemical etching using KOH or choline stops on (111)faces which form during undercutting along (110) edges on a (100)surface. The resultant situation is shown in FIG. 11.

[0052] Afterward, the base connection 25 is formed by means ofdifferential epitaxy on the uncovered regions of the base. In this case,it is particularly preferred for a highly doped (>1 10²⁰), in particulara P+ doped, base connection 25 to be used as the base connection. Theselective epitaxy is preferably effected at approximately thetemperature at which the base 14 itself was also produced (for exampleapproximately 800° C.). Accordingly, the doping profiles are notsignificantly widened in this case. Since, in this embodiment, thesidewall spacer 30 is not present in the region of the lightly dopedemitter 16, the connection 25 to the base 14 is isolated from thelightly doped emitter 16 by a pn junction.

[0053] A CVD oxide 26 is subsequently deposited and planarized. In thiscase, the residual nitride layer 22 above the emitter window is polishedaway. This is followed by the self-aligned removal of the sacrificiallayers in the emitter window. In this case, the amorphous silicon layer21 is removed in the emitter window by dry etching, the for instance CVDoxide 20 again serving as an etching stop. The resultant situation isshown in FIG. 12.

[0054] A further sidewall spacer 31 (e.g. nitride spacer) is thenproduced in order to ensure a sufficient distance between the baseconnection 25 and the n+ emitter that is still to be produced. After theoxide layer 20 has likewise been removed by wet etching using HF, the n+emitter poly 27 is deposited and patterned. The resultant situation isshown in FIG. 13.

[0055] In contrast to the bipolar transistor according to the prior artas shown in FIG. 15, in the case of the bipolar transistor according tothe invention as shown in FIG. 13, a part of the base connection 25 isessentially monocrystaline and forms a pn junction with the (111) stopfaces of the lightly doped emitter 16. In the case of the bipolartransistor according to the prior art as shown in FIG. 15, the sidewallspacer has to be produced by a phototechnology, with the result that athickness of less than 200 μm is generally not possible. This results inhigher parasitic capacitances. In the case of the bipolar transistoraccording to the invention as shown in FIG. 13, the inwardly directedsidewall spacer 31 can be introduced in a self-aligned manner into theemitter hole already present and can thus also be made very thin, forexample thinner than 50 nm.

1. A method for fabricating a bipolar transistor, in particular an npnbipolar transistor, having the following steps: a) a semiconductorsubstrate with a collector, a base and a lightly doped emitter layer isprovided; b) a mask is applied to the lightly doped emitter layer; c)the lightly doped emitter layer is etched wet-chemically with the aid ofthe mask, thereby forming a lightly doped emitter; d) a base connectionis formed on the uncovered regions of the base; e) the mask is removedand a highly doped emitter is formed.
 2. The method as claimed in claim1, characterized in that a highly doped silicon-germanium base is usedas the base.
 3. The method as claimed in claim 1 or 2, characterized inthat the mask comprises an oxide layer, a silicon layer and a nitridelayer.
 4. The method as claimed in one of the preceding claims,characterized in that the lightly doped emitter layer is etchedwet-chemically using an alkaline etchant, in particular KOH, cholineand/or ethylenediamine.
 5. The method as claimed in one of the precedingclaims, characterized in that the lightly doped emitter layer is formedabove the base as an essentially monocrystaline layer and thewet-chemical etching stops on (111) faces in said essentiallymonocrystaline layer.
 6. The method as claimed in one of the precedingclaims, characterized in that a sidewall spacer, preferably a nitridespacer, is produced before the wet-chemical etching on the side walls ofthe mask.
 7. The method as claimed in one of claims 1 to 5,characterized in that a sidewall spacer, preferably a nitride spacer, isproduced before the formation of the base connection on the side wallsof the mask and of the lightly doped emitter.
 8. The method as claimedin one of the preceding claims, characterized in that the baseconnection is formed by means of selective epitaxy on the uncoveredregions of the base.
 9. The method as claimed in one of the precedingclaims, characterized in that a sidewall spacer, preferably a nitridespacer, is produced before the formation of the highly doped emitter onthe side walls of the emitter window.
 10. A bipolar transistor, inparticular an npn bipolar transistor, with a semiconductor substrate(10), a collector (12), a base (14), a lightly doped emitter (16) and ahighly doped emitter (27), characterized in that the connection (25) tothe base (14) is oriented essentially parallel to the lightly dopedemitter (16) and is isolated from the lightly doped emitter (16) by asidewall spacer (23) or a pn junction and is formed at least in regionson the base (14).
 11. The bipolar transistor as claimed in claim 10,characterized in that the base (14) is designed as a highly dopedsilicon-germanium base.
 12. The bipolar transistor as claimed in claim10 or 11, characterized in that the base (14) has a doping, inparticular a p⁺-type doping, of more than 2 10¹⁹ per cubic centimeter.13. The bipolar transistor as claimed in one of claims 10 to 12,characterized in that the lightly doped emitter (16) has a doping, inparticular an n-type doping, of less than 2 10¹⁸ per cubic centimeter.14. The bipolar transistor as claimed in one of claims 10 to 13,characterized in that the lightly doped emitter (16) is designed as anessentially monocrystaline layer and is laterally bounded by (111)faces.
 15. The bipolar transistor as claimed in one of claims 10 to 14,characterized in that the sidewall spacer (23) is designed as a nitridespacer.
 16. The bipolar transistor as claimed in one of claims 10 to 15,characterized in that the base connection (25) is of monocrystalinedesign at least in regions.
 17. The bipolar transistor as claimed in oneof claims 10 to 16, characterized in that the base connection (25) is ahighly doped, in particular a P+ doped, base connection.
 18. The bipolartransistor as claimed in one of claims 10 to 17, characterized in thatthe collector (12) is in contact with a buried layer (11).